1. Field of the Invention
The present invention relates generally to content addressable memory devices, and more particularly, to semiconductor memory devices having a bit matching function and to a method of refreshing and partially writing on array basis in such semiconductor devices.
2. Description of the Background Art
FIG. 11 is a block diagram showing an entire structure of a cache system using a conventional CAM (Content Addressable Memory).
In FIG. 11, a main memory 101 and a cache memory 103 are connected to a CPU 106 through a data bus 104 and an address bus 105. A dynamic RAM or a magnetic disc device is used as the main memory 101. Although the magnetic disc device has a relatively long access time, it has a large capacity and is inexpensive. As the cache memory 103, a CAM is used. Although the CAM has a small capacity, it has a short access time. The cache memory 103 is provided to shorten the access time of the main memory 101. Of the data stored in the main memory 101, those which are accessed with high frequency are stored in the cache memory 103 together with the addresses thereof. The writing and the comparing operations of the cache memory 103 are controlled by a memory controller 102.
In a system structured as described above, the cache memory 103 is accessed prior to the access of the main memory 101 by the CPU 106. More specifically, when an address signal is outputted from the CPU 106 to the address bus 105, the cache memory 103 is controlled by the memory controller 102 to check whether the address corresponding to the address signal is stored in the cache memory 103 or not. If the corresponding address is stored in the cache memory 103, a hit signal 103a is outputted from the cache memory 103 and applied to the memory controller 102. When the hit signal 103a is applied from the memory controller 102 to the CPU 106, data is read out from a region corresponding to be region where the address is stored in the cache memory 103. If the address corresponding to the address signal outputted from the CPU 106 is not stored in the cache memory 103, no hit signal 103a is applied and the main memory 101 is accessed.
The above described cache memory 103 comprises a plurality of content addressable memory cells. The CAM cell has, in addition to a general writing and reading function, a matching function for comparing data stored in the memory cell with externally applied retrieval data in order to determine whether they are matching with each other or not.
In the article, "Content-Addressable Memories" by T. Kohonen, p. 143, a complete CAM organization is described, and in the same article, p. 257, an example of a cache memory using a CAM is described.
FIG. 12 is a circuit diagram of a conventional CAM cell disclosed in "IEEE Journal of Solid-State Circuit", Vol. sc-7, pp. 366 and in U.S. Pat. No. 3,701,980.
As shown in FIG. 12, the CAM cell comprises five n channel MOS transistors 1 to 5. The transistor 1 is connected between a bit line 6 and a storage node 20, and the transistor 2 is connected between an inversion bit line 7 and an inversion storage node 21, the gate of each of the transistors 1 and 2 being connected to a word line 8. The transistor 3 is connected between the bit line 6 and a control node 9 and the transistor 4 is connected between the inversion bit line 7 and the control node 9. A gate of the transistor 3 is connected to the storage node 20 and a gate of the transistor 4 is connected to the inversion storage node 21. The transistor 5 is connected between a match line 10 and the control node 9, a gate of which the transistor 5 being connected to the match line 10.
Now, the writing, matching, reading and refreshing operations of the CAM cell of FIG. 12 will be described. In the following description, "H" (logical high) indicates a power supply potential Vcc or a potential approximate thereto, and "L" (logical low) indicates a ground potential Vss or a potential approximate thereto, wherein Vcc&gt;Vss. In addition, data of the bit line pair 6 and 7 being "0" is equivalent to a potential on the bit line 6 being at the "L" level and a potential on the inversion bit line 7 being at the "H" level, and data of the bit line pair 6 and 7 being "1" is equivalent to the potential on the bit line 6 being at the "H" level and the potential on the inversion bit line 7 being at the "L" level.